1. Field of the Invention
The present invention generally relates to digital signal level shifters. More particularly, a digital signal voltage level circuit which is designed for higher density and more reliable operation without the problems of voltage bouncing and latch-up.
2. Description of the Prior Art
In the prior art, MOS transistors of which a voltage level shifter consists are connected to a node or the other node. The mechanism of a voltage level shifter is based on a feedback from the voltage of the node to the voltage of the other node. Thus a MOS transistor driving the node where the feedback starts should be strong, and then the size of the layout becomes large. And a low signal is input to the gate of an NMOS transistor where the drain is already low level, and then the voltage of the drain goes down to less than the low level through capacitor coupling of the gate capacitor. Thus a latch-up can be happen in the NMOS transistor.
It is therefore an object of the present invention to provide a circuit and a method for level shifting a digital voltage signal. It is further an object of this invention to achieve this digital signal voltage level shifter with the fastest speed, smallest density and less latch-up probability. This invention is achieved by a circuit with two extra NMOS and two extra PMOS transistors compared with the prior voltage level shifter. The extra transistors are used for avoiding floating of nodes which happens when an input of the voltage level shifter is being changed. Because of the extra transistors, a feedback which is a basic mechanism of a voltage level shifter works well, then smaller transistors call be used. Moreover, a voltage bouncing which causes latch-up can be reduced in the voltage level shifter circuit of the present invention because the extra transistors pull up or down node voltages in the opposite direction of voltage bouncing caused by capacitor coupling in other MOS transistors.